How to Read a Thermal Resistance Rating

Intel lists a case-to-ambient slope of 0.180 K/W for the Xeon Platinum 8180 on a 2U heatsink, with local ambient at 47 °C. Multiply the slope by the 205 W thermal design power, add the ambient, and the result is 83.9 °C against a published case limit of 84 °C. The same guide gives a 1U heatsink a slope of 0.255 K/W, and a Texas Instruments application note shows a package’s junction-to-ambient figure moving by as much as 50% when only the test board changes. The arithmetic is simple; the conditions attached to it are what sheets leave out.

A K/W rating is a temperature difference per watt between two named points

Thermal resistance is the temperature difference between two defined points divided by the heat flowing between them: R = ΔT / P. A kelvin and a degree Celsius are the same size, so a difference expressed in K/W and in °C/W is the same number. The rating is empty until both endpoints are named. Junction to ambient and case to coolant inlet are different quantities that share one unit.

Junction temperature is the anchor for all of them. Texas Instruments defines it as the hottest temperature of the silicon chip inside the package. The same note records that JEDEC, NEBS and AEC each place the ambient sensor in a different location, so a figure measured against one ambient does not transfer to another.

Source: Texas Instruments, “Semiconductor and IC Package Thermal Metrics,” SPRA953D (revised March 2024), Sections 1 and 7

The symbol on the sheet carries a second distinction. θ denotes a true resistance, where the stated heat actually crosses the path. Ψ denotes a characterization parameter that divides by total device power even though only part of that power crosses the path. TI states that ΨJT is not a true thermal resistance, because the heat reaching the package top during the JESD51-2 test is unknown. For plastic packages it gives ΨJT of 0.5 to 2 °C/W against RθJC of 4 to 15 °C/W.

Source: Texas Instruments, SPRA953D, Section 3

I read a Ψ value as a calibration constant for back-calculating junction temperature from a surface thermocouple, not a resistor to stack with θ values from other paths.

Stages add in series only when one path carries nearly all the heat

Series addition is exact when every stage carries the same heat, and Intel builds its server definitions that way. ΨCS is (TCASE − TS) divided by total package power, ΨSA is (TS − TLA) divided by the same power, and ΨCA is (TCASE − TLA) divided by it again. The case-to-sink and sink-to-ambient terms sum to the case-to-ambient term by construction, not by approximation.

Source: Intel, “Intel Xeon Processor Scalable Family Thermal Mechanical Specifications and Design Guide,” 336064-004US (December 2019), Table 1-2

The shortcut fails for packages that shed heat into the circuit board. TI calls RθJA = RθJC + RθCA obsolete for modern plastic packages. It reports that 70% to 95% of chip power leaves through the test board in still-air JEDEC measurements. With two paths in parallel, TI’s more accurate estimate combines the series stack (RθJC + RθCS + RθSA) with RθJA the way parallel resistors combine.

Source: Texas Instruments, SPRA953D, Sections 1.1, 2.2 and Equation 6

Assume a package with RθJA of 40 °C/W on its board, and a heatsink stack whose series sum is 10 °C/W.

Parallel combination: (40 × 10) / (40 + 10) = 400 / 50 = 8 °C/W

At 2 W, series only: 10 °C/W × 2 W = 20 K above ambient

At 2 W, parallel: 8 °C/W × 2 W = 16 K above ambient

The inputs are illustrative, not values for a specific part. The series-only estimate errs hot. That is harmless for a lidded server processor under a large heatsink. On small board-mounted parts such as voltage regulators, the board is the main path, and a series stack describes the wrong circuit.

Source: Texas Instruments, SPRA953D, Equations 5 and 6 (arithmetic by this publication)

Intel’s case temperature profile is a K/W target, and its published limits reproduce

Intel specifies case temperature for single-die Xeon Scalable parts as a straight line, y = mx + b. The slope m is ΨCA and the intercept b is local ambient, TLA. Both are published, so the case limit can be recomputed.

TCASE at TDP = ΨCA × TDP + TLA

Xeon Platinum 8180, 2U: 0.180 K/W × 205 W = 36.9 K; 36.9 K + 47 °C = 83.9 °C. Listed TCASE_MAX: 84 °C.

Xeon Platinum 8176, 1U: 0.255 K/W × 165 W = 42.075 K; 42.075 K + 47 °C = 89.075 °C. Listed TCASE_MAX: 89 °C.

Each result matches the listed limit to within rounding. extends the check to six parts across three boundary conditions, and all six reproduce.

Table 1. One metric, three boundary conditions: Xeon Scalable ΨCA targetsK/W, °C

* Computed by this publication from the listed slope and intercept; shown to 0.1 °C

* TLA is local ambient just upstream of the heatsink, not room or cold-aisle air

* Sorted by ΨCA; slopes use total package power

Source: Intel, “Intel Xeon Processor Scalable Family Thermal Mechanical Specifications and Design Guide,” 336064-004US, Table 5-1 (December 2019)

Source: Intel, 336064-004US, Section 5.2.1.1 and Table 5-1 (arithmetic by this publication)

The 8176 is allowed a case temperature of 89 °C while the 8180, on the same 47 °C intercept, stops at 84 °C. TCASE_MAX is an output of the heatsink Intel assumed for each form factor, not a fixed property of the silicon.

The intercept moves too. Shadow-core parts, which sit in another processor’s exhaust, carry intercepts of 50 to 57 °C, while spread-core parts carry 46 or 47 °C. Intel measures TLA just upstream of the heatsink, so the intercept already includes air heated inside the chassis. For a facility engineer, this intercept is where supply air temperature enters the equation, and it sits well above the cold aisle.

Source: Intel, 336064-004US, Tables 1-2 and 5-1

A cold plate rating includes the coolant’s own warming, so it needs a flow rate

The Open Compute Project cold plate white paper defines cold plate thermal resistance as R = (Tc − TL) / Q. Tc is the processor case temperature and TL is the fluid temperature at the cold plate inlet. The paper directs that R be measured at multiple flow rates, and it caps fluid velocity into the cold plate at 1.5 m/s to prevent erosion.

Source: Open Compute Project, “White Paper: Cold Plate Development and Qualification” (Intel, Inspur and contributors), Sections 1.2.2 and 1.3.2.1

Referencing the inlet means the rating contains the coolant’s temperature increase across the plate. An energy balance sizes that share.

Governing equation: ΔT_coolant = Q / (ṁ × cp)

Assumptions: water, cp = 4,180 J/(kg·K), density 997 kg/m³ (assumed property values near 25 °C), flow 1.0 L/min

Mass flow: ṁ = 1.0 L/min × 0.997 kg/L ÷ 60 s/min = 0.01662 kg/s

Heat-carrying rate: ṁ × cp = 0.01662 kg/s × 4,180 J/(kg·K) = 69.5 W/K

Mean fluid temperature sits halfway between inlet and outlet, so the coolant term is 1 / (2 × 69.5 W/K) = 0.0072 K/W at 1.0 L/min. Doubling flow to 2.0 L/min halves it to 0.0036 K/W.

This is a mean-temperature estimate, not a measured value. Beside Intel’s air-side ΨCA of 0.180 K/W it is small. In a liquid stack where every stage is measured in hundredths of a kelvin per watt, it becomes a visible share, and a cold plate figure quoted without its flow rate cannot be compared with another.

Source: Open Compute Project, cold plate white paper, Equation 1 (arithmetic by this publication)

Interface materials add a unit problem. The PTM7950 product page lists thermal impedance two ways: below 0.04 °C·cm²/W “at no shim” in its overview, and 0.04 to 0.08 °C·cm²/W at no shim, ASTM D5470 Modified, in its specification table. It also states that 30 to 40 psi of pressure is needed for use.

Source: Solstice Advanced Materials (formerly Honeywell), “PTM7950” product page (accessed September 2026)

That figure is area-normalized impedance, not K/W. Divided over an assumed 10 cm² contact area, 0.04 to 0.08 °C·cm²/W becomes 0.004 to 0.008 K/W, so the gap between the page’s two statements is a factor of two before any assembly effect. Intel specifies a TIM2 activation pressure of 137.9 kPa (20 psi) and notes that phase change materials are very sensitive to applied pressure. Intel also states that the heat spreader does not spread heat over the entire lid, so dividing by full lid area gives a lower bound on interface resistance, not a typical value.

Source: Intel, 336064-004US, Sections 2.1, 4.1 and 4.2

What to check before comparing two sheets

A thermal resistance number is comparable only when its test fixture matches. TI’s modeled data for one 128-pin TQFP package shows ΨJT of 0.09 °C/W on a 2s2p board in still air and 0.47 °C/W with an exposed pad on a 1s0p board at 250 LFM. That is a fivefold spread for one package, and TI separately reports up to 50% RθJA variation from the 1s versus 2s2p test board alone.

Source: Texas Instruments, SPRA953D, Section 1.2 and Table 3-1

Before comparing two ratings, confirm four things:

1. The two endpoints, and where the ambient or inlet sensor sits.
2. The symbol. θ adds along a single path; Ψ back-calculates from a measured surface.
3. The condition: board type and airflow for packages, flow rate for cold plates, pressure and contact area for interface materials.
4. The power basis. Intel’s Ψ values divide by total package power, and a sheet that divides by a different power produces a different slope.

These sources have limits. The Intel figures come from a 2019 guide for a 2017 processor family, and newer Xeon generations were not checked. TI’s ΨJT table is modeled. The OCP paper defines a method without reference values. The coolant and interface arithmetic rests on the stated assumptions. Sizing a thermal solution with these methods requires engineering review against the vendor’s current specification.

Low power, altitude and sensor placement

Why can the same package show a higher RθJA at low power

TI reports that RθJA falls as power increases, because a hotter package surface loses heat more efficiently by convection and radiation. At very low power, RθJA is sometimes 2× to 3× higher than at rated power. TI’s lab also measured a 10% to 20% improvement in RθJA between 0 °C and 100 °C ambient.

Source: Texas Instruments, SPRA953D, Sections 1.6 and 1.7

Does altitude change a thermal resistance rating

Yes, for air-cooled paths. TI cites IBM work showing a device running 20% hotter at 8,000 ft than at sea level. The derating factors TI reproduces run from 1.1 at 3,000 ft to 1.2 at 8,350 ft, applied to sea-level RθJA.

Source: Texas Instruments, SPRA953D, Section 1.5 and Table 1-2

Can a processor’s digital thermal sensor replace a case thermocouple

Not for verifying case temperature. Intel states there is no one-to-one correlation between TCASE and the digital thermal sensor reading. It also states that the only accurate way to determine TCASE is a thermocouple at the geometric center of the heat spreader’s top surface.

Source: Intel, 336064-004US, Sections 1.4 and 5.2.1.1

References

Semiconductor and IC Package Thermal Metrics, SPRA953D / Texas Instruments / December 2003, revised March 2024 / https://www.ti.com/lit/an/spra953d/spra953d.pdf

Intel Xeon Processor Scalable Family Thermal Mechanical Specifications and Design Guide, 336064-004US / Intel Corporation / December 2019 / https://www.intel.com/content/dam/www/public/us/en/documents/guides/xeon-scalable-thermal-guide.pdf

White Paper: Cold Plate Development and Qualification / Open Compute Project / https://www.opencompute.org/documents/ocp-cold-plate-development-and-qualification-with-integrated-comments-pdf

PTM7950 product page / Solstice Advanced Materials (formerly Honeywell) / undated web page / https://ws.solstice.com/us/en/products/advanced-semiconductor-materials/thermal-management/phase-change-materials/ptm7950