Microfluidic Cooling Cuts the Layers Between Die and Coolant

Two published tests of single phase water cooling at heat fluxes of 1 kW/cm² and above differ by more than an order of magnitude in what a watt of pumping buys. Lawrence Livermore National Laboratory (LLNL) cooled a straight-channel silicon carbide sink carrying 250 W with up to 3.7 W of pumping power.

A 2020 Nature paper by van Erp and colleagues reports heat fluxes above 1.7 kW/cm² for 0.57 W/cm² of pumping power, a ratio near 3,000. The Nature device feeds coolant through a manifold, and whether that explains the gap is open. The gap is the second half of a trade that begins with the layers between die and coolant.

Interface layers cap cold plate performance

A cold plate is a liquid-cooled metal block clamped onto the processor package, so heat reaches the water only after crossing every layer in between. Microsoft’s September 2025 announcement says most GPUs in today’s data centers are cooled this way and that the packaging layers act like blankets, holding heat in and keeping cold out. A 2013 DARPA conference paper states that the sequential conductive resistances of such remote cooling had produced only limited improvement in junction to ambient resistance over the previous decade.

Those layers can be priced. An article by an Indium Corporation author in the 2026 IEEE EPS newsletter gives experimental resistance ranges, per interface, for three families of metal thermal interface material. A lidded package has two interfaces, die to lid and lid to cold plate, and a lidless one has a single interface between die and plate. A cold plate’s own rating already folds the interface in, as the piece on cold plate thermal resistance shows from the OCP and ASHRAE definitions.

The arithmetic below applies those ranges to a real accelerator. NVIDIA lists the H100 SXM5 at up to 700 W and its GH100 die at 814 mm².

• Average flux: q″ = 700 W ÷ 8.14 cm² = 86 W/cm². Module power includes memory that sits beside the die, so this overstates the die average, and it says nothing about hot spots.
• Temperature across one interface: ΔT = R″ × q″, with R″ in K·cm²/W.
• Thin solder, R″ = 0.02 to 0.08: ΔT = 1.7 to 6.9 K.
• Compressible metal, R″ = 0.05 to 0.15: ΔT = 4.3 to 12.9 K.
• Gallium-based liquid metal, R″ below 0.05: ΔT below 4.3 K.

A single interface can therefore take between 1.7 and 12.9 K at this flux, and a lidded package puts two in series before the plate’s own convective resistance is counted. In chip cooling through embedded microchannels removes interfaces from that sum instead of trimming each term, which is why the DARPA and Microsoft texts aim at the layers and not at the water.

Heat flux quotes depend on heated area

A 2013 DARPA paper describes ICECool Applications targets of 1 kW/cm² chip heat flux for embedded computing modules, with hot spots up to 2 kW/cm². Four laboratory results now sit on either side of that mark, and the table below puts them on common axes.

Table 1. Embedded microchannel results and the area each flux is quoted over (Heat flux in W/cm²)

* Flux basis differs by row; the Micromachines value is defined over the gate region only. Nature values are from the abstract. Reference temperatures differ (coolant inlet versus room).

Source: van Erp et al., Nature 585 (2020), abstract; Micromachines (2025), doi 10.3390/mi16080908; Cassada et al., LLNL-JRNL-844626 (2023)

The Micromachines cooler reached its 1,200 W/cm² on a GaN amplifier chip, and the flux is defined over the gate region only. Total test power was 1.823 W.

• Gate region: 0.744 mm × 0.204 mm = 0.1518 mm² = 0.001518 cm², and 1.823 W ÷ 0.001518 cm² = 1,200 W/cm².
• Whole chip, 1.044 mm × 0.779 mm = 0.00813 cm²: 1.823 W ÷ 0.00813 cm² = 224 W/cm².
• The 6.0 mm × 7.0 mm microchannel structure, 0.42 cm²: 1.823 W ÷ 0.42 cm² = 4.3 W/cm².

The LLNL sink carried 250 W, about 137 times that power. Quoting both as roughly 1 kW/cm² hides two orders of magnitude in the heat each cooler has to remove.

Thermal resistance needs the same care, because a rating is empty until both endpoints are named. LLNL reports the 1981 Tuckerman and Pease sink as 71 K above a 23 °C inlet at 790 W/cm², and measures its own sink from heater to inlet water.

• Tuckerman and Pease: 71 K ÷ 790 W/cm² = 0.090 K·cm²/W.
• Micromachines: 27.9 K ÷ 1,200 W/cm² = 0.023 K·cm²/W.
• Both scaled to the 86 W/cm² of the previous section: 0.090 × 86 = 7.7 K, and LLNL’s 0.024 × 86 = 2.1 K.

The Micromachines value lands next to LLNL’s 0.024, but its reference is room air at 18.7 °C, not coolant inlet, and its flux sits at the gate.

On the same footing a whole embedded sink costs 2.1 to 7.7 K, against 1.7 to 12.9 K for one metal interface. The ranges overlap. A thin solder bond costs no more than a microchannel sink at this flux, and the advantage appears against compressible interfaces, or once the plate’s convective term is added on the other side of the ledger.

A forty-fold pumping gap between two designs

LLNL’s two silicon carbide geometries use straight channels about 6 mm long, and the paper reports the isentropic pumping power at each geometry’s highest flow rate. Isentropic means the ideal hydraulic minimum, so a real pump draws more.

• Geometry 2: 72.13 psi × 6,894.76 Pa/psi = 497,300 Pa, or 0.50 MPa.
• Flow: 0.450 kg/min ÷ 60 = 7.5 g/s, which is 7.5 × 10⁻⁶ m³/s at an assumed density of 1,000 kg/m³.
• Pumping power: 497,300 Pa × 7.5 × 10⁻⁶ m³/s = 3.73 W, against the 3.704 W the paper reports.
• Coolant temperature rise at 250 W: ΔT = 250 W ÷ (0.0075 kg/s × 4,180 J/(kg·K)) = 8.0 K, taking water at 4,180 J/(kg·K).
• Heat per pumping watt at 250 W: 250 ÷ 3.704 = 67.5 for geometry 2, and 250 ÷ 3.304 = 75.7 for geometry 1.
• Van Erp et al.: 1,700 W/cm² ÷ 0.57 W/cm² = 2,982.
• Ratio of the two data sets: 2,982 ÷ 75.7 = 39 and 2,982 ÷ 67.5 = 44.

The Nature abstract also states a coefficient of performance above 10,000 for single phase water at fluxes above 1 kW/cm². If COP there means heat flux divided by pumping power per area, the implied pumping power is 0.1 W/cm² or less. The abstract does not define COP, and the article is paywalled, so that reading is an assumption.

The same abstract compares its result with straight microchannels and calls the gain 50-fold. That implies a straight-channel baseline near 200 on the COP definition, about three times LLNL’s 67.5, and the abstract does not describe the baseline. The two papers’ straight-channel numbers cannot be reconciled from the text available.

LLNL attributes a gap between simulated and measured pressure at geometry 2’s highest flow to channels that broke before that test, so the 72.13 psi may come from a damaged part. Its authors add that wider channels at higher flow reach a similar resistance at much lower pressure drop, so the 3.7 W marks a point on a trade curve and not a floor.

The pumping share follows from the same inputs.

• LLNL: 3.704 W ÷ 250 W = 1.5%, which is 10.4 W on a 700 W accelerator.
• Nature: 0.57 ÷ 1,700 = 0.034%, which is 0.23 W on a 700 W accelerator.

Neither test used a GPU, so the 700 W lines illustrate the ratios and do not predict a device. Neither paper shows that the manifold feed alone explains the gap. The Micromachines authors, for their part, state that their design’s flow and pressure can be met by standard miniature liquid-cooling pumps, with flow no higher than 7 mL/s and pressure below 500 kPa.

Microsoft’s two figures may share one ratio

Microsoft’s announcement of September 23, 2025 reports lab-scale tests in which microfluidic cooling removed heat up to three times better than cold plates, depending on workloads and configurations. It also says the maximum temperature rise of the silicon inside a GPU fell by 65 percent, a value that will vary by chip.

The page publishes no absolute temperature, power, heat flux, flow rate, coolant, or pumping power. That rules out a row in the table above, and it limits what the two figures can be turned into.

• A 65% smaller rise leaves 1 − 0.65 = 0.35 of the cold plate rise.
• At equal power, ΔT = P × R, so the resistance ratio is 1 ÷ 0.35 = 2.86.
• At equal temperature rise, the same ratio lets power rise by a factor of 2.86.

Under two assumptions, constant resistance and the same coolant reference temperature, “up to three times better” and “65 percent” are one ratio read two ways. Microsoft does not say so, and its qualifier about workloads means the three-times figure may come from a different case than the 65 percent.

The announcement calls microfluidics not a new concept and says getting it to work has been the hard part across the industry. It lists four design iterations in the past year, a leak-proof package, and a manufacturing process for the etching as work it needed. Its stated next steps are to investigate how the technique can enter future generations of its own chips and to keep collaborating with fabrication and silicon partners to bring microfluidics into production. This is research-stage technology. No source read for this piece gives a date, and the piece supplies none.

Doubts a lab ratio leaves open

Can the 65 percent be applied to another GPU? Microsoft says the reduction varies by chip type, and the announcement gives no baseline rise. A percentage of an unpublished number cannot be converted into degrees or into a warmer coolant setpoint. The 2.86 ratio is the only quantity the page supports, and it describes one lab case.

Does cooling inside the die remove the facility loop? No source says so. Microsoft says the coolant need not be nearly as cold, which concerns supply temperature and not the heat load. The load stays in the water: at the LLNL flow, 250 W warms the coolant by about 8 K. That heat still has to be rejected downstream.

Is any of this available to buy? Microsoft describes lab-scale tests and a plan to work toward production with partners. The Micromachines authors list long-term reliability studies as future work toward commercial deployment. The Nature and LLNL devices are laboratory parts, and LLNL’s silicon carbide channels broke between tests. None of the documents gives a date, so the sourced answer stops at research stage.

Half a megapascal now loads the silicon

Moving the wetted surface from a copper plate into the die moves the pressure with it. Both designs sit near half a megapascal: 0.50 MPa across the LLNL channels, and below 500 kPa in the Micromachines cooling layer.

The Micromachines paper rates its gold-tin bond at 50 MPa, a 100-to-1 margin over that pressure. Both pressure figures describe the structure on paper and neither is a leak test.

The geometry shows what that pressure acts on.

• LLNL geometry 2: channels 416 µm deep in a heat sink nominally 0.5 mm thick, so 500 − 416 = 84 µm of floor under the channels (nominal minus measured, so approximate).
• Same geometry: channels 29.0 µm wide between fins 58.6 µm wide, an aspect ratio of 14.3.
• Micromachines: each deep etch is 260 ± 10 µm into a 525 µm wafer, 260 ÷ 525 = 50%.

The LLNL authors describe silicon carbide as extremely brittle and confirm that channels broke between tests after the test sections were removed and reinserted. Microsoft says its channels must be deep enough to circulate coolant without clogging yet not so deep that the silicon weakens and risks breaking. The interface layers degrade too: the Indium article names pump-out, dry-out, and voids for greases and some phase-change materials, and cracking and delamination for metal ones. A channeled die fails by cracking, with coolant on the wrong side of the crack.

The evidence has holes. The Nature numbers come from its abstract because the article is paywalled, so the COP definition and the heated area were unavailable. Microsoft’s figures are a company announcement of lab-scale tests, and no independent measurement appears in the sources read. The interface ranges come from one supplier’s article and apply per interface. The 86 W/cm² arithmetic assumes uniform flux, whereas a lid spreads heat sideways, which lowers the flux at the lid to plate interface and leaves die hot spots higher. The Tuckerman and Pease row comes through LLNL’s summary and not the 1981 paper. Reliability, cost, and coolant quality are not quantified anywhere in these documents, and any design decision needs qualified engineering review.

The case for embedding the channels rests on one scaling. Interface resistance multiplies with flux like everything else in the stack, so the layers matter more as flux rises.

• At 1,000 W/cm², one interface at R″ = 0.02 to 0.15 K·cm²/W gives ΔT = 20 to 150 K.
• LLNL’s entire sink at 0.024 K·cm²/W gives 24 K at the same flux.

At the 86 W/cm² average the two columns overlap, and at 1,000 W/cm² they separate by a wide margin, provided the interface actually sees that flux. That separation is the problem DARPA named in 2013, and it is why the Microsoft and Nature results matter even though neither is a product.

The conditions attached to that gain are the part the headline numbers skip. Straight channels at this flux spent about 1.5% of the heat load on pumping, and the Nature manifold device spent roughly 0.03%. The structure then carries half a megapascal through a floor tens of micrometers thick. The figure hardest to carry over to a design discussion is Microsoft’s 65 percent, which has no baseline. The ratios in this piece each have their inputs on the page.

Microfluidic cooling reads as a credible answer to a flux problem that cold plates have not met, supported by laboratory evidence only. The interface layers are removable, the pumping cost was 1.5% of the load in the straight-channel test and about 0.03% in the manifold one, and the price is mechanical risk that none of these documents measures at production scale.

References

• AI chips are getting hotter. A microfluidics breakthrough goes straight to the silicon to cool up to three times better. / Microsoft Source / 2025-09-23 / https://news.microsoft.com/source/features/innovation/microfluidics-liquid-cooling-ai-chips/
• Co-designing electronics with microfluidics for more sustainable cooling (abstract; full text paywalled) / van Erp, Soleimanzadeh, Nela, Kampitsis, Matioli, Nature 585, 211-216 / 2020-09-09 / https://www.nature.com/articles/s41586-020-2666-1
• SiC Microchannel Heat Sinks for High Heat Flux Dissipation of 1 kW/cm2 (LLNL-JRNL-844626) / Cassada et al., Lawrence Livermore National Laboratory, accepted for IEEE Transactions on Components, Packaging and Manufacturing Technology / 2023-01-31 / https://www.osti.gov/servlets/purl/2008197
• Design and Fabrication of Embedded Microchannel Cooling Solutions for High-Power-Density Semiconductor Devices / Micromachines (MDPI), doi 10.3390/mi16080908 / 2025-08-04 / https://pmc.ncbi.nlm.nih.gov/articles/PMC12388327
• Thermal Interface Materials (TIM) Strategy for Thermal Management in AI and HPC Applications / Jie Geng, Indium Corporation, IEEE EPS Newsletter / 2026 / https://eps.ieee.org/wp-content/uploads/2026/03/M-and-P-TC-Thermal-Interface-Materials-TIM-Strategy-for-Thermal-Management-in-AI-and-HPC-Applications-2026-IEEE-EPS-Newsletter_Final_YL2.pdf
• DARPA’s Intra/Interchip Enhanced Cooling (ICECool) Program / Bar-Cohen, Maurer, Felbinger, CS MANTECH Conference / 2013-05 / https://csmantech.org/wp-content/acfrcwduploads/field_5e8cddf5ddd10/post_2558/050.pdf
• NVIDIA Hopper Architecture In-Depth / NVIDIA Technical Blog / 2022-03-22 / https://developer.nvidia.com/blog/nvidia-hopper-architecture-in-depth/
• NVIDIA H100 Tensor Core GPU (product page, specifications table) / NVIDIA / undated / https://www.nvidia.com/en-us/data-center/h100/